Digital Design (m/f/d)

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• Development and implementation of RTL designs using SystemVerilog
• Implementation of technical requirements based on specifications provided by Lead Engineers and Concept Engineers
• Independent execution of design sign-off activities within the customer's internal design flow
• Execution and analysis of simulations to ensure functional correctness of the design
• Performing linting, CDC, and RDC analyses
• Creation and optimization of synthesis constraints
• Execution of MMMC synthesis and scan insertion activities
• Performing LEC, CLP, and ATPG coverage analyses
• Close interaction with internal digital designers to ensure smooth knowledge transfer
• Coordination with cross-functional teams including Analog Design, Verification, and System/Concept Engineering

• Several years of project experience in RTL design using SystemVerilog
• Strong expertise in PLLs and other clocking circuits
• Very good understanding of CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing)
• Experience in creating and optimizing synthesis constraints
• Experience with MMMC synthesis methodologies
• Good understanding of scan testing
• Independent and structured working style
• High degree of ownership and accountability for technical tasks
• Strong team player with experience working in multidisciplinary project environments
• Experience with Cadence synthesis flows is considered an advantage
• Knowledge of UPF and CLP is considered an advantage
• Experience with ATPG analysis is considered an advantage
• Experience with high-speed serial interfaces such as USB is considered an advantage

• Continuous support during the assignment

Ihr Kontakt

Ansprechpartner
Patrick Thomas Marolt

Referenznummer
894698/1

Kontakt aufnehmen
E-Mail: patrick.marolt@hays.at

Anstellungsart
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