Verification Engineer (m/f/d)

Our many years of recruitment experience and our expert knowledge of the engineering job market make us a strong partner for engineers and technicians. We maintain close relationships with customers across all industries and therefore can provide engineering specialists with exciting projects and attractive job opportunities, drawing on your personal interests and experience. As your professional companion, we support you throughout the entire process, from the first contact to the first day on your new job – all this completely free of charge. Register now and look forward to many interesting and suitable positions and projects.

• Planning, developing, and executing verification strategies for IP and SoC components
• Creating and maintaining verification environments using Specman E and UVM
• Applying SystemVerilog assertions for formal and dynamic verification
• Analyzing and debugging RTL code using Verilog constructs
• Supporting TLM model debugging using C++
• Running simulations and regression tests using Cadence tools (Xcelium, Specman-elite, SimVision, vManager)
• Documenting and reviewing verification results

• More than 8 years experience in multiple project verification sign-off (both IP and SoC verification)
  
• Specman E language and UVM methodology expertise
  
• Hands on experience with SystemVerilog assertions
  
• Understanding of ARM-AMBA protocols / Verilog constructs to debug RTL issues / C++ constructs to debug tlm models
• Working experience with Cadence simulation/regression tools (Xcelium, Specman-elite, SimVision, vManager)
• Desirable: Experience on requirement-based verification for ISO/safety projects / Experience with Graphics processing IPs / Experience with Formal Property checking and other automated tools

• Continuous support during the assignment

Ihr Kontakt

Ansprechpartner
Ada Florence Willared

Referenznummer
821811/1

Kontakt aufnehmen
E-Mail: ada.willared@hays.de

Anstellungsart
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